[新竹]SOC Digital Implementation Designer

職務說明

SOC-PI team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GDS: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow except DFT and P&R Join us, you will work together with expertise in all these areas; you will not only work for physical implementation, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing: - Netlist generation and STA analysis - Synthesis, Netlist quality check, Formal Verification and constraints creation and validation, timing budget. - Co-work with PD engineers to implement chip partition and floorplan - Work in conjunction with RTL designer and PD engineers to achieve timing closure for both partition and full chip level - Achieve special timing closure, such as io, test, clock etc. - Flow automation development, Methodology in any of above areas. What we need to see: - BSEE, MSEE is preferred - Project experience in IC design implementation - Courses taken in circuit design, digital design - Hand-on experience in EDA software from Synopsys (DC/FC/PT/Formality), Cadence (LEC) is preferred Ways to stand out from the crowd: - Proficient user of Perl, Python or TCL is preferred - Excellent English communication skill