G260095-Physical Design Technical Manager

Job description

Key Responsibilities -Lead netlist-to-GDS physical implementation activities, including floorplanning, placement, clock tree synthesis (CTS), routing, power optimization, timing optimization & signoff. -Primary technical interface for customers. Ensure project requirements, design targets, and implementation strategies are well defined and aligned. -Drive execution across different functional teams to ensure design quality, key milestone achievement, and successful project delivery. Identify design bottlenecks, propose optimization strategies, and coordinate with stakeholders to improve design PPA. -Coaching & mentoring of fresh/junior engineers Minimum qualifications -Master's or Ph. D degree in Electrical/Electronics Engineering, Computer Science, or a related field. -8 years of experiences in relevant domain. -Proficiency with Cadence Innovus or Synopsys ICC2/FusionCompiler. -Experiences with sub-28nm FinFET nodes (16/12/7nm) implementation. -Strong understanding of digital design fundamentals, timing analysis, and physical implementation flows. -Excellent communication skills, analytical & debugging capability, and a teamwork mindset. Preferred qualifications -Experiences with leading-edge process nodes (5/3/2nm) is a plus. -Familiarity with physical verification and power integrity tool such as Voltus, RedHawk, Calibre, or equivalent. -Experiences in customer-facing technical discussions. -Fluent in English. TOEIC 730-855 is preferred; TOEIC 855+ is a plus.