[新竹]SoC Technology Enablement & DTCO Engineer (various levels)

職務說明

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! You will join our growing Global Advanced Technology Enablement team that is specialized in driving technology development across Samsung System LSI business. We engage with Foundry partners from the very early phase to thoroughly explore target technology for next-generation SoC products. Samsung System LSI values the strategic importance of DTCO/TE activities, especially for advanced technology beyond 5nm nodes. Our goal is to maximize Samsung LSI’s product benefits, often measured by PPA, Silicon Reliability, and design TAT. You will join us in a senior technical lead role that drives Foundry/EDA/Foundation IP (FIP)-Development to unlock new technology potential, which is key towards our business success. What you’ll do： -You conduct in-depth comparisons of PPA across various foundry process technologies to guide technology selection and optimization -You evaluate and analyze foundry PDKs, identifying key changes and assessing their impact on design and manufacturing workflows -You get excited about overseeing general DTCO activity from early TD up to tape-out and revision. -You are passionate about Foundation IP (FIP) Architecture exploration for new technology. This includes coordinating with the global FIP design team (both in-house and Foundry). -You understand Advanced Methodology development, ranging from Physical Design (P&R), transistor-level/circuit Layout, Signoff, Electrical/Physical Verification up to DFM. You will help our team coordinate with global design methodology teams and will often directly drive global R&D teams from various EDA vendors. -You pride yourself on identifying and distilling complex problems or situations by seeking the root causes and engaging others to brainstorm possible outcomes. -You are skilled at driving future-oriented changes and generating creative perspectives and solutions. You bring fresh ideas to challenge past practices, approaches, and old ways of thinking to introduce new innovation opportunities. -You thrive on driving cross-company collaboration with a global perspective. You enjoy helping our team collaborate with internal and external partners to drive technology enablement, while harnessing our diversity as a strength to achieve business results. Skills And Qualifications： -Proven expertise in PPA analysis and optimization within semiconductor foundry environments -Strong understanding of foundry PDKs, including their development, evaluation, and management -10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a PhD -Technology Enablement (TE) and DTCO experience at advanced technology nodes (below 5nm). The activity includes technology, logic and memory cell architecture exploration, and interconnect option exploration. Multiple-Foundry experience is a big plus. -Foundation IP (both Library Cell and SRAM Memory) design and architecture experience up to MTO and post-Silicon activity. -Experienced in Physical Design (e.g., Synthesis and P&R), PDN design, library exploration, Signoff, EDA tools, transistor-level parasitic extraction, circuit simulation, etc. EDA interfacing experience, especially for driving new technology features, is a plus. - Experienced related to SPICE simulation or DRC, or with a background in circuit layout.