[新竹]CPU&NPU Design Implementation Engineer (RTL to GDS)

職務說明

SOC-XPU team is hiring both junior and senior engineers, whose work scope is CPU&NPU physical implementation from RTL to GDS: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, congestion analysis, short fixing, PV, IR and also all related flows. Join us, you will work together with expertise in all these areas; you will not only work for physical implementation, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing： -Responsible for CPU/NPU block-level RTL to GDS implementation -Perform synthesis, netlist generation, and static timing analysis (STA) -Conduct formal verification, constraint development, and timing budgeting -Drive timing closure across partitions and full-chip level, including special paths (I/O, test, clock domains) -Execute place and route (PnR) flow including floorplan, placement, CTS, routing, and physical verification -Debug and resolve physical design issues such as congestion, DRC violations, and timing failures -Contribute to methodology improvements for XPU design efficiency and quality What we need to see： -BSEE or MSEE degree (preferred) -Solid experience in XPU or SoC IC design implementation -Academic background in digital circuit design and computer architecture -Hands-on experience with EDA tools such as Synopsys (DC, FC, PT, Formality) and Cadence (Genus, Innovus) Ways to stand out from the crowd： -Proficiency in scripting languages like Perl, Python, or TCL -Familiarity with XPU microarchitecture and pipeline design -Experience with full-chip PnR and timing closure